//! Register definitions for the RK3588 PWM controller.

/// Register offsets from the channel base address.
pub mod offset {
    /// Current counter value.
    pub const COUNTER: usize = 0x00;
    /// Period register.
    pub const PERIOD: usize = 0x04;
    /// Duty cycle register.
    pub const DUTY: usize = 0x08;
    /// Control register.
    pub const CTRL: usize = 0x0c;
}

/// Control register bit definitions.
pub mod ctrl {
    /// Enable PWM output.
    pub const ENABLE: u32 = 1 << 0;
    /// Continuous mode selector.
    pub const CONTINUOUS: u32 = 1 << 1;
    /// Duty output polarity positive.
    pub const DUTY_POSITIVE: u32 = 1 << 3;
    /// Inactive output polarity positive.
    pub const INACTIVE_POSITIVE: u32 = 1 << 4;
    /// Center-aligned output selection.
    pub const OUTPUT_CENTER: u32 = 1 << 5;
    /// Lock configuration registers.
    pub const LOCK_EN: u32 = 1 << 6;
    /// Mask covering duty and inactive polarity bits.
    pub const POLARITY_MASK: u32 = (1 << 3) | (1 << 4);
    /// Bit mask used when enabling/disabling the PWM (matches Linux driver
    /// behaviour).
    pub const ENABLE_CONF_MASK: u32 = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 5) | (1 << 8);
    /// Default configuration bits to enable left-aligned continuous output.
    pub const ENABLE_CONF_DEFAULT: u32 = (1 << 0) | (1 << 1);
    /// Bit shift for the oneshot count field.
    pub const ONESHOT_COUNT_SHIFT: u32 = 24;
    /// Mask for oneshot count bits.
    pub const ONESHOT_COUNT_MASK: u32 = 0xff << ONESHOT_COUNT_SHIFT;
    /// Maximum oneshot repetition count supported by the hardware.
    pub const ONESHOT_COUNT_MAX: u16 = 256;
}

/// RK3588 PWM controller uses a prescaler value of 1 according to the vendor
/// driver.
pub const RK3588_PRESCALER: u32 = 1;
